1. Field of the Invention
The present invention relates to a logic simulation apparatus which simulates the logic operation of a logic circuit designed by a circuit designer using a computer system. The logic simulation apparatus according to the present invention is realized by dedicated hardware which can execute logic simulation at a high speed. Further, the logic simulation apparatus according to the present invention includes a highly reliable system which can easily perform error analysis during simulation process.
2. Description of the Related Art
Before providing a logic circuit by actual hardware and starting actual production of the circuit, it is necessary to simulate logic operation of the designed logic circuit in order to confirm whether it provides the desired performance. Particularly, since large scale and very complicated logic circuits are now used in computer systems, it is very important to simulate such logic circuits at a high speed before producing actual hardware.
A logic simulation apparatus is used for simulating such logic circuit using a computer system. That is, the logic circuit to be simulated (i.e., a model logic circuit) is provided in the logic simulation apparatus, and a certain test pattern is input to the logic circuit to check the operation thereof.
In general, logic simulation is realized by using software on a computer system. However, recently, logic simulation is performed using dedicated hardware to realize a high-speed simulation process. A logic simulation apparatus according to the present invention is realized by using dedicated hardware to achieve high speed logic simulation process.
Further, there are known three representative algorithms for dedicated hardware for logic simulation, i.e., a level-sorting method, an exhaustive method, and an event driven method. The present invention is mainly used for the event driven method.
In the dedicated hardware for logic simulation, it is necessary to increase the size of the dedicated hardware in accordance with the size of the logic circuit to be simulated. Accordingly, for example, the dedicated hardware used for simulation of a general purpose computer, a super computer, etc., becomes very large and expensive.
Further, conventional dedicated hardware for logic simulation is used for only one simulation process, and cannot be used for another simulation process at the same time. Accordingly, throughput of the dedicated hardware falls because another simulation process must wait until completion of previous simulation process.
Still further, for example, if a very large dedicated hardware is used for a small simulation process, utilization efficiency of the dedicated hardware falls.